Evolve Your FPGA Verification Methodology with Formal & Clock Domain Crossing

Free online session about Evolving your FPGA Verification Methodology with Formal & Clock Domain Crossing

Attention FPGA Designers:

Did your last FPGA design stretch beyond the project schedule?
Did your last FPGA have post production identified defects?
Did your last FPGA require more than 3 iterations of lab debug?

Attend this free online session to learn how Questa Formal with Autocheck and Clock Domain Crossing (CDC) can provide you with the needed solution to achieve your verification goals.

When

Monday the 24th of October 2016 and Tuesday the 15th of November 2016:  14:00 – 15:00 CEST