Questa™ Base packs unprecedented verification capabilities in a cost-effective HDL simulation solution. Its award-winning single kernel simulator (SKS) technology enables the transparent mixing of VHDL and Verilog in one design. Questa Base simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the standard delay format (SDF). The Questa Base architecture allows platform-independent compilation with the outstanding performance of native compiled code. Design quality and debug productivity are improved with the state-of-the-art Visualizer debug solution.
Edit, recompile and re-simulate very easily – Download Fact Sheet
The graphical user interface is powerful, consistent, and intuitive. You can edit, recompile and re-simulate without leaving the Questa Base environment. All windows update automatically following activity in any other window. For example, selecting a design region in the structure window automatically updates the source, signals, process, and variables windows. All user interface operations can be scripted, and simulations can run in batch or interactive modes.
