Tanner AMS IC design flow (formerly HiPer Silicon AMS IC design flow) supports analog/mixed-signal design in one highly-integrated, end-to-end flow. Engineers can perform top-down, mixed-signal simulation or co-simulation, synthesis with DFT support, place and route, and high-speed, “sign-off ready” timing analysis for tape-out, within one cost-effective, unified flow.
- OpenAccess, LEF/DEF, Liberty and SDF support
- Simulate combined netlists: behavioral models, block-level RT/gate and transistor-level blocks
- Debugging and support of advanced verification with SystemC and System Verilog
- Proven, compatible synthesis with DFT support
- Hierarchical DRC and netlist extraction with Calibre® compatibility
- All-angle design rule checking (DRC) with interactive and real-time DRC
- Foundry PDK support
Visit our website for more information or give us a call (45) 898 823 42
