You can still register for the Verification Workshop in Copenhagen.
Following on the online seminars about “FPGA Verification Methodology with Formal & Clock Domain Crossing” and “UVM VIP – Evolve your FPGA Verification Methodology” we invite you to attend the free Verification workshop.
In the morning you will learn how to use the push-button formal tools Questa AutoCheck and Questa CDC. You will also learn how to debug and fix bugs and how to use a metastability model created by Questa CDC.
In the afternoon you will learn how to create an UVM environment by using the UVM Framework. You will also learn how to create an UVM environment with the Questa Verification IP configurator. The last lesson is how to resuse both environments in a toplevel environment.
You can register for one or both workshops.
